Browsing by Author "Aguiar, Rui L."
Now showing 1 - 6 of 6
Results Per Page
Sort Options
- Clock Repeater Characterization for Jitter-Aware Clock Tree SynthesisPublication . Figueiredo, Monica; Aguiar, Rui L.This paper presents a simple jitter model for clock repeaters. The model is scalable and technology independent, which makes it suitable for integration in current clock tree synthesis algorithms. It is based on the timing characterization of a reference inverter, which can be performed for different process corners to account for process variability. Simulation results show that the model is accurate to within 10% for the most common inverter and NAND based repeaters.
- Dynamic jitter accumulation in clock repeaters considering power and ground noise correlationsPublication . Figueiredo, Mónica; Aguiar, Rui L.This paper discusses the mechanism behind dynamic jitter accumulation in clock repeaters, considering the impact of power supply noise correlations. We show that differential and common mode noise have a different impact on jitter accumulation, depending on correlations between cascaded repeater stages. We also propose a simple accumulation model that can be used to replace time-consuming transient noise simulations. Besides providing an useful insight regarding the impact of noise correlations on jitter accumulation, the model's accuracy is shown to be within 10% of SPICE results.
- A dynamic jitter model to evaluate uncertainty trends with technology scalingPublication . Figueiredo, Mónica; Aguiar, Rui L.Clock jitter can no longer be considered negligible when compared to clock skew. Its unpredictability and high-frequency content makes it an increasingly limiting factor to performance in modern digital systems. In this paper, we investigate dynamic jitter and uncertainty trends, as technology continues scaling to the nanometric region. Simulation results are used to derive heuristic metrics for the sensitivity of a generic repeater to dynamic variability sources. These metrics are then used to discuss clock precision degradation with technology scaling. Using parameters that can be easily obtained, the proposed model can be useful to assess the expected behavior of existing and future technologies in terms of clock precision. Also, it provides a valuable insight regarding the key circuit parameters responsible for dynamic jitter insertion.
- A Study on CMOS Time Uncertainty with Technology ScalingPublication . Figueiredo, Mónica; Aguiar, Rui L.This paper evaluates the clock generation quality of different digital circuits associated with clock generation and distribution. Circuit’s noise response, jitter, and uncertainty are evaluated for different noise sources and loading conditions. We present performance simulations for inverters and inverter chains implemented in different technologies from AMS and UMC foundries. We show that the device size-scaling trend is increasing the uncertainty associated with this circuits, decreasing their precision. The correlation between circuit’s parameters and selected performance metrics is also highlighted.
- Time precision comparison of digitally controlled delay elementsPublication . Figueiredo, Mónica; Aguiar, Rui L.This paper compares the time precision of different digitally controlled delay cells. Other design metrics as delay, signal integrity, power and area are also considered. The precision is evaluated by the cell's uncertainty, given as the ratio between jitter and time delay, considering both thermal and power supply noise. The comparison is based on circuit simulation, in a 180nm technology, using the SPECTRE tool from Cadence. The comparison results will help the designer to choose the most appropriate delay cell for low uncertainty design.
- Uncertainty in DLL deskewing schemesPublication . Figueiredo, Mónica; Aguiar, Rui L.This paper proposes an analytical model to evaluate deskewing uncertainty, considering floorplanning and scalability issues. It can be a helpful tool in evaluating the potential gains of clock deskewing or finding the best deskewing topology for a given application, at an early design stage. Also, we show that all deskewing schemes trade static for dynamic clock uncertainty and thus, our model can be used to determine the maximum tolerable noise levels if a deskewing scheme is to be applied.