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A Jitter Insertion and Accumulation Model for Clock Repeaters
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Orientador(es)
Resumo(s)
This paper presents a model to estimate jitter insertion and accumulation in clock repeaters. We propose expressions to estimate, with low computational effort, both static and dynamic clock jitter insertion in repeaters with different sizes, interconnects and slew-rates. It requires only the pre-characterization of a reference repeater, which can be accomplished with a small number of simulations or measurements. Furthermore, we propose expressions for dynamic jitter accumulation that considers the dual nature of power and ground noise impact on delay. The complete model can be used to replace time-consuming transient noise simulations when evaluating jitter in clock distribution systems, and provide valuable insights regarding the impact of design parameters on jitter. Presented results show that our models can estimate jitter insertion and accumulation with an error within 10% of simulation results, for typical designs, and accurately reflect the impact of changing design parameters.
Descrição
Palavras-chave
Jitter Noise CMOS clock repeaters
Contexto Educativo
Citação
Mónica FIGUEIREDO, Rui L. AGUIAR, A Jitter Insertion and Accumulation Model for Clock Repeaters, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2012, Volume E95.A, Issue 12, Pages 2430-2442, Released on J-STAGE December 01, 2012, Online ISSN 1745-1337, Print ISSN 0916-8508, https://doi.org/10.1587/transfun.E95.A.2430
Editora
Institute of Electronics, Information and Communications Engineers (IEICE)
Licença CC
Sem licença CC