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Authors
Advisor(s)
Abstract(s)
This paper proposes an analytical model to evaluate deskewing uncertainty, considering floorplanning and scalability issues. It can be a helpful tool in evaluating the potential gains of clock deskewing or finding the best deskewing topology for a given application, at an early design stage. Also, we show that
all deskewing schemes trade static for dynamic clock uncertainty and thus, our model can be used to determine the maximum tolerable noise levels if a deskewing scheme is to be applied.
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Pedagogical Context
Citation
M. Figueiredo and R. L. Aguiar, "Uncertainty in DLL deskewing schemes," 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), Seville, Spain, 2012, pp. 841-844, doi: 10.1109/ICECS.2012.6463621.
Publisher
IEEE
CC License
Without CC licence