Uncertainty in DLL deskewing schemes

Figueiredo, Mónica; Aguiar, Rui L.

http://hdl.handle.net/10400.8/14564

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Autores

Figueiredo, Mónica

Aguiar, Rui L.

Resumo(s)

This paper proposes an analytical model to evaluate deskewing uncertainty, considering floorplanning and scalability issues. It can be a helpful tool in evaluating the potential gains of clock deskewing or finding the best deskewing topology for a given application, at an early design stage. Also, we show that all deskewing schemes trade static for dynamic clock uncertainty and thus, our model can be used to determine the maximum tolerable noise levels if a deskewing scheme is to be applied.

URI

http://hdl.handle.net/10400.8/14564

Citação

M. Figueiredo and R. L. Aguiar, "Uncertainty in DLL deskewing schemes," 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), Seville, Spain, 2012, pp. 841-844, doi: 10.1109/ICECS.2012.6463621.

Editora

IEEE

DOI

10.1109/icecs.2012.6463621

Coleções

ESTG - Comunicações em conferências e congressos internacionais

Licença CC

Sem licença CC

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