All-digital reconfigurable STDCC radar baseband implementation in FPGA

Duarte, Luís; Ribeiro, Carlos; Alves, Luís N.; Caldeirinha, Rafael F. S.

http://hdl.handle.net/10400.8/13783

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All-digital reconfigurable STDCC radar baseband implementation in FPGA.pdf	This paper reports the architecture of an all-digital Swept Time-Delay Cross-Correlator (STDCC) baseband. Until recently, the sliding correlator technique has been mainly em-ployed for sounding the radio propagation channel. However, recent benchmarks have shown promising results in target detection context when compared to commercially available solutions. STDCC takes advantage of the sliding correlation properties of Pseudo-Noise (PN) sequences. Therefore, this paper presents the baseband generation for this new radar technique with on-the-fly sequence tuning using a Field-Programmable Gate Array (FPGA). The reconfigurable STDCC radar baseband generates both PN sequences digitally and requires a low-cost ADC to acquire the time dilated result. At the end, the proposed architecture is evaluated regarding resource usage efficiency and then the radar performance will be discussed in terms of the all-digital PN sequence spectrum and the real-time slide correlation. Our analysis confirmed a strong correlation between both sequence length and sampling frequency with radar detectable distance.	1.84 MB	Adobe PDF	Download

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Authors

Duarte, Luís

Ribeiro, Carlos

Alves, Luís N.

Caldeirinha, Rafael F. S.

Abstract(s)

This paper reports the architecture of an all-digital Swept Time-Delay Cross-Correlator (STDCC) baseband. Until recently, the sliding correlator technique has been mainly em-ployed for sounding the radio propagation channel. However, recent benchmarks have shown promising results in target detection context when compared to commercially available solutions. STDCC takes advantage of the sliding correlation properties of Pseudo-Noise (PN) sequences. Therefore, this paper presents the baseband generation for this new radar technique with on-the-fly sequence tuning using a Field-Programmable Gate Array (FPGA). The reconfigurable STDCC radar baseband generates both PN sequences digitally and requires a low-cost ADC to acquire the time dilated result. At the end, the proposed architecture is evaluated regarding resource usage efficiency and then the radar performance will be discussed in terms of the all-digital PN sequence spectrum and the real-time slide correlation. Our analysis confirmed a strong correlation between both sequence length and sampling frequency with radar detectable distance.

Description

EISBN - 978-1-7281-6743-5
Article number - 9249556; Conference date - 20 July 2020 - 22 July 2020; Conference code - 164941

Keywords

RADAR STDCC PN sequences FPGA

URI

http://hdl.handle.net/10400.8/13783

Citation

L. Duarte, C. Ribeiro, L. N. Alves and R. F. S. Caldeirinha, "All-digital reconfigurable STDCC radar baseband implementation in FPGA," 2020 12th International Symposium on Communication Systems, Networks and Digital Signal Processing (CSNDSP), Porto, Portugal, 2020, pp. 1-6, doi: https://doi.org/10.1109/CSNDSP49049.2020.9249556.