Substrate noise isolation improvement in a single-well standard CMOS process

Santos, P. Mendonça dos; Moreira Mendes, Luís Miguel; João Caldinhas Vaz

http://hdl.handle.net/10400.8/13380

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Authors

Santos, P. Mendonça dos

Moreira Mendes, Luís Miguel

João Caldinhas Vaz

Abstract(s)

This work describes a fully CMOS compatible methodology, which makes available a pseudo deep n-well in single-well standard CMOS process. The proposed method is based on mask manipulation to accommodate the field implant p-type region into the n-well, and does not require any additional masks or modification in the CMOS process flow. According to the experimental results, the floating NMOS made available by the methodology shows a reduction in the threshold voltage, which implies a slight improvement in its performance, when compared with its standard NMOS counterpart. It was also experimentally demonstrated up to 3 GHz, that the guard-ring field implant/pseudo deep n-well proposed structure improves substrate noise isolation when compared to the classical p+ guard-ring, with a maximum improvement above 20 dB for low frequencies and a minimum of 4 dB at 3 GHz.

Keywords

CMOS technology MOSFET Integrated circuit noise

URI

http://hdl.handle.net/10400.8/13380

Citation

P. Mendonça dos Santos, Luís Mendes, João Caldinhas Vaz, Substrate noise isolation improvement in a single-well standard CMOS process, Integration, Volume 52, 2016, Pages 122-128, ISSN 0167-9260, https://doi.org/10.1016/j.vlsi.2015.09.006