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Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis

2010Conference paper Open access
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datacite.subject.fosCiências Naturais::Matemáticas
datacite.subject.fosCiências Naturais::Ciências da Computação e da Informação
datacite.subject.sdg03:Saúde de Qualidade
datacite.subject.sdg07:Energias Renováveis e Acessíveis
datacite.subject.sdg11:Cidades e Comunidades Sustentáveis
dc.contributor.authorFigueiredo, Monica
dc.contributor.authorAguiar, Rui L.
dc.date.accessioned2025-11-26T17:18:33Z
dc.date.available2025-11-26T17:18:33Z
dc.date.issued2010
dc.descriptionFonte: https://www.researchgate.net/publication/220799307_Clock_Repeater_Characterization_for_Jitter-Aware_Clock_Tree_Synthesis
dc.descriptionConference name - 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009; Conference date - 9 September 2009 - 11 September 2009; Conference code - 79934
dc.descriptionEISBN - 9783642118029
dc.description.abstractThis paper presents a simple jitter model for clock repeaters. The model is scalable and technology independent, which makes it suitable for integration in current clock tree synthesis algorithms. It is based on the timing characterization of a reference inverter, which can be performed for different process corners to account for process variability. Simulation results show that the model is accurate to within 10% for the most common inverter and NAND based repeaters.eng
dc.identifier.citationFigueiredo, M., Aguiar, R.L. (2010). Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_9.
dc.identifier.doi10.1007/978-3-642-11802-9_9
dc.identifier.eissn1611-3349
dc.identifier.isbn9783642118012
dc.identifier.isbn9783642118029
dc.identifier.issn0302-9743
dc.identifier.urihttp://hdl.handle.net/10400.8/14748
dc.language.isoeng
dc.peerreviewedyes
dc.publisherSpringer Nature
dc.relation.hasversionhttps://link.springer.com/chapter/10.1007/978-3-642-11802-9_9
dc.relation.ispartofLecture Notes in Computer Science
dc.relation.ispartofIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
dc.rights.uriN/A
dc.subjectJitter Model
dc.subjectClock Repeaters
dc.subjectCTS
dc.titleClock Repeater Characterization for Jitter-Aware Clock Tree Synthesiseng
dc.typeconference paper
dspace.entity.typePublication
oaire.citation.conferenceDate2009-09
oaire.citation.conferencePlaceDelft, The Netherlands
oaire.citation.endPage10
oaire.citation.startPage1
oaire.citation.titleLecture Notes in Computer Science
oaire.versionhttp://purl.org/coar/version/c_ab4af688f83e57aa
person.familyNameFigueiredo
person.givenNameMónica
person.identifier.orcid0000-0002-0780-3725
relation.isAuthorOfPublicationb31235fc-ac6f-4b97-8665-ad80c78f79d7
relation.isAuthorOfPublication.latestForDiscoveryb31235fc-ac6f-4b97-8665-ad80c78f79d7

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This paper presents a simple jitter model for clock repeaters. The model is scalable and technology independent, which makes it suitable for integration in current clock tree synthesis algorithms. It is based on the timing characterization of a reference inverter, which can be performed for different process corners to account for process variability. Simulation results show that the model is accurate to within 10% for the most common inverter and NAND based repeaters.
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