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Uncertainty in DLL deskewing schemes

dc.contributor.authorFigueiredo, Mónica
dc.contributor.authorAguiar, Rui L.
dc.date.accessioned2025-11-07T15:32:46Z
dc.date.available2025-11-07T15:32:46Z
dc.date.issued2012-12
dc.description.abstractThis paper proposes an analytical model to evaluate deskewing uncertainty, considering floorplanning and scalability issues. It can be a helpful tool in evaluating the potential gains of clock deskewing or finding the best deskewing topology for a given application, at an early design stage. Also, we show that all deskewing schemes trade static for dynamic clock uncertainty and thus, our model can be used to determine the maximum tolerable noise levels if a deskewing scheme is to be applied.eng
dc.identifier.citationM. Figueiredo and R. L. Aguiar, "Uncertainty in DLL deskewing schemes," 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), Seville, Spain, 2012, pp. 841-844, doi: 10.1109/ICECS.2012.6463621.
dc.identifier.doi10.1109/icecs.2012.6463621
dc.identifier.issn978-1-4673-1260-8
dc.identifier.urihttp://hdl.handle.net/10400.8/14564
dc.language.isoeng
dc.peerreviewedn/a
dc.publisherIEEE
dc.relation.hasversionhttps://ieeexplore.ieee.org/document/6463621/keywords#keywords
dc.relation.ispartof2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)
dc.rights.uriN/A
dc.titleUncertainty in DLL deskewing schemeseng
dc.typebook part
dspace.entity.typePublication
oaire.citation.endPage844
oaire.citation.startPage841
oaire.versionhttp://purl.org/coar/version/c_970fb48d4fbd8a85
person.familyNameFigueiredo
person.givenNameMónica
person.identifier.orcid0000-0002-0780-3725
relation.isAuthorOfPublicationb31235fc-ac6f-4b97-8665-ad80c78f79d7
relation.isAuthorOfPublication.latestForDiscoveryb31235fc-ac6f-4b97-8665-ad80c78f79d7

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