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Browsing by Author "Duarte, Luís"

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  • All-digital reconfigurable STDCC radar baseband implementation in FPGA
    Publication . Duarte, Luís; Ribeiro, Carlos; Alves, Luís N.; Caldeirinha, Rafael F. S.
    This paper reports the architecture of an all-digital Swept Time-Delay Cross-Correlator (STDCC) baseband. Until recently, the sliding correlator technique has been mainly em-ployed for sounding the radio propagation channel. However, recent benchmarks have shown promising results in target detection context when compared to commercially available solutions. STDCC takes advantage of the sliding correlation properties of Pseudo-Noise (PN) sequences. Therefore, this paper presents the baseband generation for this new radar technique with on-the-fly sequence tuning using a Field-Programmable Gate Array (FPGA). The reconfigurable STDCC radar baseband generates both PN sequences digitally and requires a low-cost ADC to acquire the time dilated result. At the end, the proposed architecture is evaluated regarding resource usage efficiency and then the radar performance will be discussed in terms of the all-digital PN sequence spectrum and the real-time slide correlation. Our analysis confirmed a strong correlation between both sequence length and sampling frequency with radar detectable distance.
    2020-07Conference paper Open access Show more
  • Multi-Gigabit/s OFDM real-time based transceiver engine for emerging 5G MIMO systems
    Publication . Ribeiro, Carlos; Gomes, Rodolfo; Duarte, Luís; Hammoudeh, Akram; Caldeirinha, Rafael F. S.
    This paper presents a highly scalable multi-Gigabit/s Real-Time (RT) Wideband (WB) Orthogonal Frequency Division Multiplexing (OFDM) processing chain for 5G applications. It is aimed to significantly reduce the Hardware (HW) footprint of Multiple Input Multiple Output (MIMO) systems. In this context, implementation complexity results for MIMO configurations of 2 × 2, 4 × 4 and 8 × 8, enabled at sampling rates of 245.76, 122.88, 61.44 and 30.72 MHz, respectively, are compared with the ones from conventional MIMO architectures. For example, for a 8 × 8 MIMO–OFDM configuration implementation, savings of up to 87% are achieved when compared with conventional design methods, in terms of DSP48E1 slices. Moreover, in a Xilinx Virtex 7 XC7VX485T, it is shown that a second processing branch might be implemented, leading to a 5 Gbps (using 1024 Quadrature Amplitude Modulation (QAM)) Single-Input Single-Output (SISO) link or a 16 × 16 MIMO configuration. Finally, in order to validate the proposed architecture, the impact of its inclusion on a complete Field Programmable Gate Array (FPGA) 8 × 8 OFDM system, at LTE's highest sampling rate of 30.72 MHz, is evaluated. Subsequently, it is demonstrated that this does not affect the performance of OFDM, even in the presence of Carrier Frequency Offset (CFO).
    2020-02Journal article Open access Show more