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Performance, power and scalability analysis of HEVC interpolation filter using FPGAs

datacite.subject.fosEngenharia e Tecnologia
datacite.subject.sdg09:Indústria, Inovação e Infraestruturas
dc.contributor.authorGomez-Pulido, Juan A.
dc.contributor.authorCordeiro, Paulo J.
dc.contributor.authorAssunção, Pedro
dc.date.accessioned2025-06-27T09:42:35Z
dc.date.available2025-06-27T09:42:35Z
dc.date.issued2015-10
dc.descriptionArticle number 7313689
dc.description.abstractMotion compensation is the most time-consuming stage of the most recent video coding standard, and uses an interpolation filter to handle efficiently the video bitstream. When high resolutions, low power budgets and huge amount of video data are demanded, exploiting parallelism is a mandatory task. In this paper we propose an implementation of the interpolation filter using the reconfigurable hardware technology, in order to build parallel computing systems that offer a high performance, in terms of computing time and power consumption. The timing simulations and energy analysis performed on different devices show that the on-chip replication of the filter provides high speedups with regard to general purpose processors. The good experimental results motivates us to do a first approach to scalable parallel computing systems where parallelism is exploited from fine to coarse grain, multiplying the speedups obtained. In particular, we propose an on-chip multiprocessor system where filters act as coprocessors of embedded high-performance and low-power microprocessors, linked among them by point-to-point buses. This on-chip architecture can be applied to high performance computing systems based on the same reconfigurable hardware technology.eng
dc.description.sponsorshipThis work was partially supported by Instituto de Telecomunicacões, Project UID/EEA/50008/2013, Portugal.
dc.identifier.citationJ. A. Gomez-Pulido, P. J. Cordeiro and P. A. Assunção, "Performance, power and scalability analysis of HEVC interpolation filter using FPGAs," IEEE EUROCON 2015 - International Conference on Computer as a Tool (EUROCON), Salamanca, Spain, 2015, pp. 1-6, doi: 10.1109/EUROCON.2015.7313689.
dc.identifier.doi10.1109/eurocon.2015.7313689
dc.identifier.issn978-147998569-2
dc.identifier.urihttp://hdl.handle.net/10400.8/13432
dc.language.isoeng
dc.peerreviewedyes
dc.publisherIEEE
dc.relationInstituto de Telecomunicações
dc.relation.hasversionhttps://ieeexplore.ieee.org/document/7313689
dc.relation.ispartofIEEE EUROCON 2015 - International Conference on Computer as a Tool (EUROCON)
dc.rights.uriN/A
dc.subjectFPGA
dc.subjectHEVC
dc.subjectinterpolation
dc.subjectmotion compensation
dc.subjectperformance
dc.subjectpower consumption
dc.subjectreconfigurable hardware
dc.subjectscalability
dc.subjectVideo coding
dc.titlePerformance, power and scalability analysis of HEVC interpolation filter using FPGAseng
dc.typeconference paper
dspace.entity.typePublication
oaire.awardTitleInstituto de Telecomunicações
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/UIDP%2F50008%2F2020/PT
oaire.citation.conferenceDate2015-09
oaire.citation.conferencePlaceBelgaum, India
oaire.citation.titleProceedings - EUROCON 2015
oaire.fundingStream6817 - DCRRNI ID
oaire.versionhttp://purl.org/coar/version/c_970fb48d4fbd8a85
person.familyNameAssunção
person.givenNamePedro
person.identifier.ciencia-id6811-3984-C17B
person.identifier.orcid0000-0001-9539-8311
person.identifier.ridA-4827-2017
person.identifier.scopus-author-id6701838347
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.nameFundação para a Ciência e a Tecnologia
relation.isAuthorOfPublication25649bb9-f135-48e8-8d0f-3706b86701d3
relation.isAuthorOfPublication.latestForDiscovery25649bb9-f135-48e8-8d0f-3706b86701d3
relation.isProjectOfPublication91a8e212-cbb0-462f-b533-5ed3552e8067
relation.isProjectOfPublication.latestForDiscovery91a8e212-cbb0-462f-b533-5ed3552e8067

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