Percorrer por autor "Cordeiro, Paulo J."
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- Complexity Analysis of HEVC Decoding for Multi-core PlatformsPublication . Cordeiro, Paulo J.; Assunção, Pedro; Gómez-Pulido, Juan A.The High Efficiency Video Coding (HEVC) is the latest standard, providing the same quality as its predecessor H.264/AVC at about half of the bit-rate. An increasing demand for higher quality and better resolutions in mobile applications require the use of more efficient video codecs, but the high computational complexity of HEVC poses problems to resource-constrained devices and portable equipment with limited batery-life. Despite the fact that video coding complexity is much higher than decoding, in most user devices, video decoding is used more often than encoding, thus particular attention must also be given to HEVC decoders. This paper presents an experimental study and complexity analysis of the HEVC decoder’s behaviour when decoding 4k ultra high definition (UHD) and HD video sequences on multi-core platforms, such as those of the most recent mobile devices. It is shown that when tile partitioning is used, different tiles have different decoding complexities. These findings are relevant for devising dynamic tile partitioning schemes capable of achieving load balancing in video decoders running on multi-core platforms.
- Distributed Coding/Decoding Complexity in Video Sensor NetworksPublication . Cordeiro, Paulo J.; Assunção, PedroVideo Sensor Networks (VSNs) are recent communication infrastructures used to capture and transmit dense visual information from an application context. In such large scale environments which include video coding, transmission and display/storage, there are several open problems to overcome in practical implementations. This paper addresses the most relevant challenges posed by VSNs, namely stringent bandwidth usage and processing time/power constraints. In particular, the paper proposes a novel VSN architecture where large sets of visual sensors with embedded processors are used for compression and transmission of coded streams to gateways, which in turn transrate the incoming streams and adapt them to the variable complexity requirements of both the sensor encoders and end-user decoder terminals. Such gateways provide real-time transcoding functionalities for bandwidth adaptation and coding/decoding complexity distribution by transferring the most complex video encoding/decoding tasks to the transcoding gateway at the expense of a limited increase in bit rate. Then, a method to reduce the decoding complexity, suitable for system-on-chip implementation, is proposed to operate at the transcoding gateway whenever decoders with constrained resources are targeted. The results show that the proposed method achieves good performance and its inclusion into the VSN infrastructure provides an additional level of complexity control functionality.
- Performance, power and scalability analysis of HEVC interpolation filter using FPGAsPublication . Gomez-Pulido, Juan A.; Cordeiro, Paulo J.; Assunção, PedroMotion compensation is the most time-consuming stage of the most recent video coding standard, and uses an interpolation filter to handle efficiently the video bitstream. When high resolutions, low power budgets and huge amount of video data are demanded, exploiting parallelism is a mandatory task. In this paper we propose an implementation of the interpolation filter using the reconfigurable hardware technology, in order to build parallel computing systems that offer a high performance, in terms of computing time and power consumption. The timing simulations and energy analysis performed on different devices show that the on-chip replication of the filter provides high speedups with regard to general purpose processors. The good experimental results motivates us to do a first approach to scalable parallel computing systems where parallelism is exploited from fine to coarse grain, multiplying the speedups obtained. In particular, we propose an on-chip multiprocessor system where filters act as coprocessors of embedded high-performance and low-power microprocessors, linked among them by point-to-point buses. This on-chip architecture can be applied to high performance computing systems based on the same reconfigurable hardware technology.
- A pixel-based complexity model to estimate energy consumption in video decodersPublication . Costa, Victor H.; Assunção, Pedro A. Amado; Cordeiro, Paulo J.The increasing use of HEVC video streams in diverse multimedia applications is driving the need for higher user control and management of energy consumption in battery-powered devices. This paper presents a contribution for the lack of adequate solutions by proposing a pixel-based complexity model that is capable of estimating the energy consumption of an arbitrary software-based HEVC decoder, running on different hardware platforms and devices. In the proposed model, the computational complexity is defined as a linear function of the number of pixels processed by the main decoding functions, using weighting coefficients which represent the average computational effort that each decoding function requires per pixel. The results shows that the cross-correlation of frame-based complexity estimation with energy consumption is greater than 0.86. The energy consumption of video decoding is estimated with the proposed model within an average deviation range of about 6.9%, for different test sequences.