Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis

Figueiredo, MonicaAguiar, Rui L.2025-11-262025-11-262010Figueiredo, M., Aguiar, R.L. (2010). Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_9.978364211801297836421180290302-9743http://hdl.handle.net/10400.8/14748Fonte: https://www.researchgate.net/publication/220799307_Clock_Repeater_Characterization_for_Jitter-Aware_Clock_Tree_SynthesisConference name - 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009; Conference date - 9 September 2009 - 11 September 2009; Conference code - 79934EISBN - 9783642118029This paper presents a simple jitter model for clock repeaters. The model is scalable and technology independent, which makes it suitable for integration in current clock tree synthesis algorithms. It is based on the timing characterization of a reference inverter, which can be performed for different process corners to account for process variability. Simulation results show that the model is accurate to within 10% for the most common inverter and NAND based repeaters.engJitter ModelClock RepeatersCTSClock Repeater Characterization for Jitter-Aware Clock Tree Synthesisconference paper10.1007/978-3-642-11802-9_91611-3349