Figueiredo, MónicaAguiar, Rui L.2025-04-222025-04-222009Figueiredo, M., Aguiar, R.L. (2009). A Study on CMOS Time Uncertainty with Technology Scaling. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_15.978354095947297835409594890302-97431611-3349http://hdl.handle.net/10400.8/12826Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008 - 10 September 2008 through 12 September 2008 - Code 75486This paper evaluates the clock generation quality of different digital circuits associated with clock generation and distribution. Circuit’s noise response, jitter, and uncertainty are evaluated for different noise sources and loading conditions. We present performance simulations for inverters and inverter chains implemented in different technologies from AMS and UMC foundries. We show that the device size-scaling trend is increasing the uncertainty associated with this circuits, decreasing their precision. The correlation between circuit’s parameters and selected performance metrics is also highlighted.engCMOSUncertaintyNoiseJitterScalingconference paper10.1007/978-3-540-95948-9_15